Itanium is the brand name for 64-bit Intel microprocessors that implement the Intel Itanium architecture (formerly called IA-64). Intel has released two processor families using the brand: the original Itanium and the Itanium 2. Starting November 1, 2007, new members of the second family are again called Itanium. The processors are marketed for use in enterprise servers and high-performance computing systems. The architecture originated at Hewlett-Packard (HP) and was later developed by HP and Intel together.
Itanium's architecture differs dramatically from the x86 architectures (and the x86-64 extensions) used in other Intel processors. The architecture is based on explicit instruction-level parallelism, in which the compiler makes the decisions about which instructions to execute in parallel. By contrast, other superscalar architectures depend on elaborate processor circuitry to keep track of instruction dependencies during runtime. This alternative approach helps current Itanium processors execute up to six instructions per clock cycle.
After a protracted development process, the first Itanium processor, codenamed Merced, was released in 2001, and more powerful Itanium processors have been released periodically. HP produces most Itanium-based systems, but several other manufacturers have also developed systems based on Itanium. As of 2007[update], Itanium is the fourth-most deployed microprocessor architecture for enterprise-class systems, behind x86-64, IBM POWER, and SPARC.[1] Intel released its newest Itanium, codenamed Montvale, in November 2007,[2] and has announced plans to release a quad-core Itanium processor (code-named Tukwila) to server OEMs in late 2008. Systems based on the new processor are expected to be available in early 2009,[3] more than a year later than Intel's initial projection.[4]
History Development: 1989–2001
In 1989, HP determined that reduced instruction set computer (RISC) architectures were approaching a processing limit at one instruction per cycle. HP researchers investigated a new architecture, later named explicitly parallel instruction computing (EPIC), that allows the processor to execute multiple instructions in each clock cycle. EPIC implements a form of very long instruction word (VLIW) architecture, in which a single instruction word contains multiple instructions. With EPIC, the compiler determines in advance which instructions can be executed at the same time, so the microprocessor simply executes the instructions and does not need elaborate mechanisms to determine which instructions to execute in parallel.[7] The goal of this approach is two-fold: first, to enable deeper inspection of the code to identify additional opportunities for parallel execution; and, second, to simplify processor design and reduce energy consumption by eliminating the need for runtime scheduling circuitry.
HP determined that it was no longer cost-effective for individual enterprise systems companies such as itself to develop proprietary microprocessors, so HP partnered with Intel in 1994 to develop the IA-64 architecture, which derived from EPIC. Intel was willing to undertake a very large development effort on IA-64 in the expectation that the resulting microprocessor would be used by the majority of enterprise systems manufacturers. HP and Intel initiated a large joint development effort with a goal of delivering the first product, Merced, in 1998.[7]
During development, Intel, HP, and industry analysts predicted that IA-64 would dominate in servers, workstations, and high-end desktops, and eventually supplant RISC and complex instruction set computer (CISC) architectures for all general-purpose applications. Compaq and Silicon Graphics decided to abandon further development of the Alpha and MIPS architectures respectively in favor of migrating to IA-64.[8]
Several groups developed operating systems for the architecture, including Microsoft Windows, Linux, and UNIX variants such as HP-UX, Solaris,[9] [10] [11] Tru64 UNIX,[8] and Monterey/64[12] (the latter three were canceled before reaching the market). By 1997, it was apparent that the IA-64 architecture and the compiler were much more difficult to implement than originally thought, and the delivery of Merced began slipping.[13] Technical difficulties included the very high transistor counts needed to support the wide instruction words and the large caches. There were also structural problems within the project, as the two parts of the joint team used different methodologies and had slightly different priorities. Since Merced was the first EPIC processor, the development effort encountered more unanticipated problems than the team was accustomed to. In addition, the EPIC concept depends on compiler capabilities that had never been implemented before, so more research was needed.
Intel announced the official name of the processor, Itanium, on October 4, 1999.[14] Within hours the name Itanic [15] had been coined in an online chat room, a reference to Titanic, the "unsinkable" ocean liner which sank in 1912. Itanic has since often been used by The Register,[16] Scott McNealy,[17] and others,[18][19] implying that the multibillion dollar investment in Itanium—and the tremendous early hype—would be followed by its relatively quick demise.
